1. Field of the Invention
The present invention relates to In-System Programming of programmable integrated circuits. In particular, the present invention relates to reprogramming a programmable integrated circuit in its operational environment without requiring reset of the system in which the programmable integrated circuit is a part.
2. Discussion of the Related Art
In-system programming (ISP) refers to a technique by which a programmable logic device (PLD), e.g., a complex PLD (CPLD) or a field programmable gate array (FPGA) can be reprogrammed or reconfigured without being taken out of its operational environment, such as a printed circuit board. In-System programming techniques are disclosed, for example, in U.S. Pat. No. 5,237,218, entitled xe2x80x9cStructure and Method for Multiplexing Pins for In-System Programmingxe2x80x9d to Josephson et al, and in U.S. Pat. No. 5,635,855, entitled xe2x80x9cMethod for Simultaneous Programming of In-System Programmable Integrated Circuits,xe2x80x9d to Tang et al.
Typically, upon entering ISP mode, e.g., by asserting an ISP signal, programming data and commands are shifted serially into an in-system programmable integrated circuit via a serial input pin synchronized by a programming clock signal. During programming, the input and output pins of the ISP integrated circuit are put into a xe2x80x9chigh impedancexe2x80x9d state. Consequently, output signals driven by the integrated circuit to be received into other circuits in the system become indeterminate. Thus, even though ISP can be performed without removal from the system, the system is required to be reset during and after programming to ensure proper operations. In certain applications, such reset operations interrupt service and can be difficult to carried out without manual intervention (e.g., system deployed in satellites), or can be time consuming. Thus, an ability to perform ISP without requiring a reset of the system is desired.
Many ISP integrated circuits also provide support for the IEEE 1149.1 test standard (popularly known as the xe2x80x9cboundary scanxe2x80x9d or xe2x80x9cJTAGxe2x80x9d test standard). Under the boundary scan standard, a boundary scan register is provided for each input or output pin of the integrated circuit. Each boundary scan register stores a logic value which can be driven out of the integrated circuit as an output signal of its associated output pin, or driven internally as an input signal from an input pin. One example of an implementation of the boundary scan standard in a PLD is disclosed in U.S. Pat. No. 5,412,260, entitled xe2x80x9cMultiplexed Control Pins for In-System Programming and Boundary Scan State Machines in a High Density Programmable Logic Devicexe2x80x9d to Tsui et al.
The present invention provides, in an In-system programmable (ISP) logic device, both a method and an input/output circuit which allow an output signal from a boundary scan register to be provided as output during programming operations of the ISP logic device. Thus, the ISP logic circuit can shift data through the boundary scan chain to provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system during and after reprogramming of the ISP logic device.
A method of the present invention includes: (a) providing, in the programmable logic circuit, a scan chain formed out of boundary scan registers associated with a number of input/output pins; and (b) providing a state machine for controlling both programming operations of the programmable logic circuit and boundary scan operations of the scan chain. The state machine configures the scan chain such that data in the boundary scan registers are provided to the input/output pins when the programming operations are carried out.
According to one aspect of the present invention, the state machine executes a number of instructions, including an instruction which both initiates a programming operation of the programmable logic circuit and configures the scan chain to allow data shifting in the scan chain. In one embodiment, the programming operation is not terminated when a subsequent instruction for shifting data into and out of the scan chain is executed. In that embodiment, the state machine executes another instruction for terminating the initiated programming operation.
In one embodiment, the initiated programming operation programs a predetermined number of architecture cells in the programmable logic circuit. In another embodiment, the initiated programming operation erases a predetermined number of architecture cells in the programmable logic circuit.
According to another aspect of the present invention, an ISP logic device of the present invention includes: (a) a programmable logic circuit providing a number of output signals; and a number of output circuits each including: (i) an input/output pin; (ii) a boundary scan register providing an output signal; and (iii) a multiplexer, which receives one of the output signals from the programmable logic circuit and the output signal from the boundary scan register. The multiplexer is configured to provide on the output pin, in response to a control signal indicating that the ISP logic device is being programmed, the output signal from the boundary scan register. The boundary scan registers of the output circuits can be configured to form a scan chain receiving serial input data from a serial input pin and providing serial output data at a serial output pin.
In one embodiment, the ISP logic device further includes a state machine providing the control signal to the multiplexer in accordance with a second control signal received at an input pin.
In another embodiment, the output pin of the output circuit is implemented as a bidirectional interface circuit which can be configurable to receive an input signal and to provide the input signal as input to the programmable logic circuit, even when the ISP logic device is being programmed.
The state machine of the ISP logic device controls both programming operation of the programmable logic circuit and operations of the scan chain. That state machine allows operations of the scan chain to be active simultaneously with the programming operations.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.